Approaches and tools for security in software and hardware development and assessment

Expected Outcome:Proposals are expected to contribute to one or more of the following:Enhanced security frameworks for both hardware and software supply chains, building on root-of-trust architectures and secure lifecycle management;Secure and trusted chip architectures for next-generation computing and networking systems;Integrated security-by-design approaches in software development, aimed to be aligned with relevant regulatory requirements;Security testing methodologies, including formal verification approaches and AI-driven security testing methodologies;Standardised methodologies for hardware security assessment, also contributing to cybersecurity certification. Scope:The increasing complexity and globalisation of software and hardware supply chains introduce new vulnerabilities that cyber adversaries can exploit. Ensuring the security of both software and hardware components across the lifecycle of digital systems is paramount. This topic aims to develop innovative tools, methods, and processes to secure the entire ecosystem of software and hardware development.Proposals should explicitly select one main area of focus but can also address both:a. Secured hardware systems over trusted ChipsThe security of modern computing infrastructures relies heavily on the robustness of hardware components. This subtopic aims to develop robust security solutions for trusted hardware platforms, focusing on secured microprocessors, secure boot mechanisms, and cryptographic acceleration. Proposals are also expected to address the risks of hardware-based vulnerabilities and backdoors, ensuring the security of devices from edge to cloud, also taking into account emerging threats, including quantum where relevant. Synergies with existing EU initiatives on trusted hardware (e.g., CHIPS JU, EuroHPC) are encouraged. The topic is expected to:Develop new architectures for tamper-resistant chips and processors. Exploring novel designs for secure microprocessors, leveraging hardware-lev